ANALYSIS OF AREA DELAY OPTIMIZATION OF IMPROVED SPARSE CHANNEL ADDER

Abstract

With the revolution in integrated circuits, great emphasis was given on performance and miniaturization. Speed, area
and power became the main criterion upon which a VLSI system is measured in terms of its efficiency. In any VLSI
system, a full adder is widely component, which decides the performance of the system. The design and analysis of a
modified Carry Select Adder(CSLA) is proposed in a cadence 45nm CMOS. It reduces the gate count, thereby area is
reduced. Based on modification in CSLA, the process is performed in an efficient way in terms of its gate count and
thereby on power and speed