ANALYSIS OF HYBRID FULL ADDER TOPOLOGIES BASED ON IMPROVED DRPTL

Abstract

Recently adder circuit is becoming a major part in many applications and the arithmetic circuit is included in it as a fundamental operation. Basically the adder circuit is designed to achieve low power and less delay and by logic gate of the circuit improves the performances. In this paper, for significant process of power saving and efficient performances Hybrid Full Adder Topologies is proposed dynamically based on dual rails pass transistor logic (DRPTL) with the clock signal. For speed process high logic circuit is implemented and also to have less propagation. In hybrid CMOS design style various adder cells and transistor is used, but in proposed circuit DRPTL is implemented with the load condition and the clock signal to manage the power flow in the circuit. Also enhance the device performances and reduce the chip level power consumption. The proposed circuit is simulated for the analysis of performances by the implementation in Cadence Virtuoso Schematics on 45nm CMOS process models and illustrated the results performances delay, power, and transistor count reduction.