A LOW POWER RECODING METHODOLOGY FOR THE DESIGN OF A MAC UNIT USING FUSED ARCHITECTURE

Abstract

The paper presents a new fused methodology proposed for the MAC unit in 65nm which consumes less power, area and reduces the
critical path delay. This paper focuses on the efficient design of Fused adder-multiply operators, targeting the optimization of the recoding
scheme for direct shaping of the Modified Booth form of the sum of two numbers. More specifically, we propose new technology
advancement compared to the recoding technique available in 90nm technology. The proposed technology decreases the critical path delay
and reduces the power consumption. The proposed technology not only reduces the power but area also been reduced. The work is done for
different fused approach using conventional and signed-bit Adders as building blocks. The implementation is done using Spice models,
results are observed and power analysis is made.