A NOVEL CIRCUIT METHODOLOGY TO IMPROVE THE TRANSITION DELAY AND PROVIDE SIGNAL FEED THROUGH FOR INPUT DATA IN PULSE TRIGGERED FLIP FLOP

Abstract

In this paper, a new method to improve the transition delay, Conditional Pulse enhancement and reduction in transistor count for Flip
Flop is proposed which consumes less power and area. The design featuring an explicit type pulse-triggered structure improves the problem
arises due to transition delay. The clocked Pseudo NMOS style structure enhances the efficiency and reduces the load capacitance. The
design which successfully solves the long discharging path problem also reduces the transistor count in the discharge path. The Proposed
circuit is implemented using Predictive technology Model in CMOS 90-nm technology. The proposed design outperforms the existing
method by reducing the power by 15% and 40% with two existing methods.