Muthu F, T.S A, T R. DESIGN OF CMOS 8-BIT PARALLEL ADDER ENERGY EFFICIENT STRUCTURE USING SRCPL LOGIC STYLE . Pak. J. Biotechnol [Internet]. 2017 Jul. 2 [cited 2024 Jul. 16];14(Special II):257-60. Available from: https://pjbt.org/index.php/pjbt/article/view/685