MUTHU, Felix; T.S, Aravinth.; T, Rajendran. DESIGN OF CMOS 8-BIT PARALLEL ADDER ENERGY EFFICIENT STRUCTURE USING SRCPL LOGIC STYLE . Pakistan Journal of Biotechnology, [S. l.], v. 14, n. Special II, p. 257–260, 2017. Disponível em: https://pjbt.org/index.php/pjbt/article/view/685. Acesso em: 26 nov. 2024.