POWER AWARE ENTROPIC HIDDEN MARKOV CHAIN ALGORITHM FOR CODE BASED TEST DATA COMPRESSION

Abstract

Even though the scan architectures generally utilize advanced designs for testing reason, most of them remain an expensive design in test data volume and power consumption. A novel software based test data compression technique for testing System on Chip (SoC) is proposed in this paper. The proposed technique concurrently addresses the problem of reducing large test data volume and reduction of power consumption for scan testing on embedded Intellectual Property (IP) cores. In comparison to the aim of reducing only test data volume by recognizing the appearance of vector patterns and thereby eliminating don't-care bits using entropic Hidden Markov Chain (HMC) algorithm, here we address the task of decreasing power consumption. The proposed power proficient test data compression method is tested using the Verilog model of ISCAS'89 and ITC'99 benchmarks.