DESIGN OF 4-BIT MULTIPLEXER USING SUB-THRESHOLD ADIABATIC LOGIC (STAL)

Abstract

Objective: This paper presents the low power consumption for Very Large Scale Integration (VLSI) design. The dynamic power consumption of CMOS circuits is continuously becoming a major concern in VLSI technique. Tool: All the simulations in this work are done using Tanner EDA Tools V14.11. Contribution & Results: In this paper the 4-Bit STAL multiplexer design have been analyzed and low power multiplexer is designed using the positive feedback logic. The STAL multiplexer is a Positive Feedback-STAL consumes less power than the CMOS multiplexer is identified from this study. Applications: In mere future the system can be enhanced to perform higher order bits.