DESIGN OF CMOS 8-BIT PARALLEL ADDER ENERGY EFFICIENT STRUCTURE USING SRCPL LOGIC STYLE

Abstract

Objectives: We present high speed and low power 8-Bit parallel adder cells designed with modified SR-CPL logic styles that had a reduced power delay product (PDP) as compared to the previous logics DPL and pass transistor logic. Tool Used: All the parallel adders were designed with a 0.18µm CMOS technology virtuoso cadence environment. Results: Simulations of the circuit show that the proposed parallel adders have reduced the power from 0.33mW to 0.24mW. Applications: In mere future the system can be implemented in high speed processors for achieving low power