DESIGN AND TESTABILITY OF Z-TERNARY CONTENT ADDRESSABLE MEMORY LOGIC

Abstract

The emerging technology using Field Programmable Gate Arrays (FPGA’s) is the leading architectures with look-up tables (LUT’s) based design plays the major role in the chip design. The memory unit and controller are the basic units and it performs the operation based on the lookup table methods. The logic circuit is designed based on requirements. The Ternary content addressable memories (TCAMs) are hardware-based parallel lookup table design with masking capability in bit level. So it is attractive for applications such as network routing and packet forwarding. The high power consumption is one of the major limitations faced by TCAM designers. This proposed design is based on the circuit techniques aiming to reduce Ternary Content Addressable Memory power consume. The Traditional TCAM table and its hybrid partitions are implemented based on the testing and verification of memory unit. The method is implemented using the normal architecture analysis. The ternary logics are implemented in shift registers, Input output