ANALYSIS OF THE EFFECT OF NBTI ON DATA FLIP TIME DEPENDENCY ON AN MTCMOS SRAM

Abstract

The predominant restraining factor of the circuits lifespan are Temperature Instability effects like NBTI and PBTI. A regular configuration to evaluate the influence of NBTI on a circuit’s operation is developed relating significant circuit constraints such as the node switching action, variation in supply voltage, temperature etc. The influence of NBTI on Read strength of SRAM cell is analyzed. Due to the NBTI stress, the working of the SRAM is totally affected. The consignment of deterioration in Static Noise Margin (SNM), is computed by the read steadiness of SRAM cells is appraised. We suggest a novel method to retrieve the SNM of SRAM cells employing a data flip process and portray the results obtained. The performance issues of the data flip time are analyzed by HSPICE simulation with varied supply voltages. The circuit design with NBTI stress is calculated depends upon the simulation setup of HSPICE tool. The supply voltage is varied by 0 V, 0.2 V, 0.4 V, 0.6 V, 0.8 V and 1 V with a length of 45nm and width of 90nm (Taken from PTM technology).