FULL CUSTOM LAYOUT OPTIMIZATION TECHNIQUES

Abstract

Design of an integrated circuit layout is said to be the characterization of the components and elements of the integrated
circuit in 3-dimension in geometrical models which represents the silicon layers, oxide layers, metal and polysilicon. Optimizing
the layout helps in producing less parasitic effects, interconnect delays, power dissipation and signal integrity in an IC. The
proposed work reduces total layout area of the application by incorporating following methods together: 1) depletion sharing, 2)
minimum distance rule and 3) different metal layers. The proposed technique is practiced on 40 transistor D-flip flop[1] layout
using Cadence® virtuoso® 64 tool. On using the minimum distance rule method along with depletion sharing the total layout
area is reduced by 71.60% and on combining all the three methods area reduces by 73.44% with reference to schematic driven
layout of example circuitry. In proposed layout, in order to subdue the reliability issue, single vias are replaced with double vias
wherever possible. Simulation after post layout is done and the corresponding power calculation has been identified for the
layout of the example circuitry and results clearly say that total layout area reduction is reducing the power consumption directly
in total.