RECONFIGURABLE MULTIPROCESSOR ARCHITECTURE FOR TURBO DECODING

Abstract

This paper presents the implementation of turbo decoder on butterfly topology and star topology for parallel processing.
Now a days turbo decoder plays major role in wireless communication like WIFI, WIMAX etc. Turbo codes are replacing the
LPDC code due to it’s higher error correcting ratio. Turbo codes are generated by the turbo encoders in the transmitter side.
During transmission turbo codes are corrupted with noise. The corrupted signal is reconstructed using turbo decoder. The
butterfly topology are implemented in turbo decoder for asynchronous load. It provides less network latency and less path
diversity. The star topology is implemented in turbo decoder for simple architecture. Turbo decoder implemented in butterfly
topology and star topology produce high throughput compared to normal turbo decoding