DESIGN AND ANALYSIS OF CYCLIC REDUNDANCY CHECK USING QUANTUM-DOT CELLULAR AUTOMATA (QCA)

Abstract

Forcommunication systems, error detectors are required to make sure that error free signal is passed while
transmitting/receiving. This error detection is resolvedby a basic parity generator and parity checker in QCA.But
these parity checkers cannot detect all forms of error. It checks whether it is an odd or even parity. To overcome the
limits of parity checker, cyclic redundancy check (CRC) will be analysed and can be designed using QCA.
Currently, QCA standsa assuring replacement for CMOStechnology. In QCA,the operation isdirected bythe
electron’s position. The consumption of power in QCA is less and the operation of clock frequency is high over
traditionalCMOS. Also with technology reaching Nano-scale, CMOS does not function perfect. CRC’s are
especially useful in digital circuits such as phase detectors, code converters and error detection & correction
circuits. In this paper, QCA Designer tool ver. 2.0.3 has been used for the simulation of the design.